Exploiting Hierarchical Configuration to Improve Run-Time MPSoC Task Assignment

Run-time assignment of a set of communicating tasks onto a heterogeneous multiprocessor system-on-chip (MPSoC) platform is a challenging task. Having FPGA fabric tiles in such MPSoC platform increases performance and flexibility of the platform. Such FPGA tiles can not only run tasks in hardware but also instantiate a soft IP core that executes the task functionality. Thus fully exploiting the available FPGA fabric resources must include exploiting such a hierarchical configuration. This paper details the benefits of using a hierarchical configuration and illustrates how to incorporate it within a generic run-time task assignment heuristic. We show that adding a hierarchical configuration significantly improves task assignment performance (i.e. success rate and assignment quality). In several cases, the performance of a heuristic with a hierarchical configuration extends beyond the capabilities of a full solution space exploration without hierarchical configuration, at only a fraction of the computation time.